Taking maximum advantage of dynamic reconfiguration in the implementation of digital systems poses a number of challenging research problems. Specifically, techniques are needed to partition the system behavioral description into segments of computation (or “scheduling units”), and to define a reconfiguration schedule with respect to those units, so as to maximize the performance of the dynamically reconfigurable system, subject to the area constraints of the FPGA. We propose a methodology to: perform a coarse-grained partitioning of the system behavioral description into a set of tasks, determine which sub-set of tasks is to remain resident in the FPGA, and which sub-set is to be non resident, generate a reconfiguration schedule for the non-resident tasks by specifying when such tasks should be loaded on to and erased from the FPGA