In this paper we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using High-level Synthesis (HLS) tools. These modern FPGA design tools accept C/C++ descriptions as input specifications, and automatically generate a Register Transfer Level (RTL) descripcion for FPGA implementation using traditional FPGA implementation tools. We have used AutoESLs AutoPilot HLS tool to implement this demanding algorithm on a Virtex-5 running at a clock frequency of 225MHz. The obtained results show that these modern high-level synthesis tools produce Quality of Results (QoR) competitive to the ones obtained using a traditional RTL design approach, while significantly abstracting the designer from the low-level FPGA implementation details.