In this study we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using high-level synthesis (HLS) tools. These modern FPGA design tools accept C/C++ descriptions as input specifications, and automatically generate a register transfer level (RTL) description for FPGA implementation using traditional FPGA implementation tools. We have used AutoESL’s AutoPilot HLS tool to implement this demanding algorithm on a Virtex-5 running at a clock frequency of 225 MHz. The obtained results show that these modern HLS tools produce Quality of Results competitive to the ones obtained using a traditional RTL design approach, while significantly abstracting the designer from the low-level FPGA implementation details.