Over the past decade, High-Level Synthesis (HLS) tools and methods have increasingly become mainstream in the strategy of leading companies in the field of FPGAs. On the one hand, HLS allows FPGA manufactures to widen the target market, smoothing the existing barriers that prevented potential users from adopting reconfigurable hardware technologies. On the other hand, HLS easies the work of system developers who benefit from integrated and automated design workflows, considerably reducing the “time to market” constrain. However, there is still some uncertainty about the quality and performance of the designs that results from the HLS processes. As the HLS tools increase the level of abstraction, it is necessary to evaluate if the incurred performance losses compensate the design time reduction. Therefore, a better understanding of HLS tradeoffs is needed to make the most of this technology. In this paper, an optimization of the high-level synthesis methodology using Vivado HLS is presented. Several options are analyzed for each alternative through the testing of the interpolators used in the Scalable Video Codec (SVC), using the Programmable Logic (PL) of the ZynQ device. Thus, an accurate evaluation on the pros and cons of this implementation is provided to allow the designers making decisions to speed-up their circuits when using this methodology.