High-Level Synthesis (HLS) allows engineers to build complex FPGA-based solutions by reducing the time-to-market; contrarily, HLS introduces some problems such as lost of control of the generated RTL and the signal observability during the development process. This fact demands an on-board debugging ecosystem so as to make HLS technology a successful approach. In this paper, HALib (Hardware Assertion Library) is introduced as a collection of synthesizable assertions that can be directly embedded into the high-level model, plus a comprehensive verification framework. HALib allows engineers to debug HLS-based modules once their have been mapped onto an FPGA by means of internal variable monitoring, avoiding any restriction regarding signal observability. Our solution has been integrated in Vivado toolchain and tested on a Zedboard with a collection of HLS kernels. The analysis of experimental results shows that the proposed solution does not incur a relevant overhead in terms of hardware resources, an increase of around 2% of FlipFlops and 1% of LUTs per assertion instantiated, neither increase the kernel delay in terms of timing