In this PhD dissertation, we propose a new testing approach for effectively managing hardware development risks, producing hardware designs with enough quality and reliability. Our proposal is based on the combination of high-level modelling and a unit testing framework in order to generate real hardware implementations for validating the designer intent, in order to keep a high cycle-accuracy and a low design effort. Such real hardware implementations are based on FPGAs, whose reconfigurability are key to provide a flexible verification environment, whereas unit testing frameworks have been extended to consider new testing requirements beyond pure functionality, such as timing analysis. Moreover, we provide a hardware library with two different types of components: 1) monitors to check internal variables at run time, keeping the errors to later trace them, and 2) double functions to reduce third-party dependencies.