High-Level Synthesis (HLS) provides a simple way to implement complex applications using Field Programmable Gate Array (FPGA) devices. Unfortunately, this technology introduces non-negligible problems related to verification: speed, accuracy and behavior mismatch between co-simulation and implementation. This paper presents RC-Unity, a heterogeneous unit testing framework that integrates FPGA-in-the-loop devices in order to extend the scope and capabilities of current HLS tools. Verification engineers can focus on the design of the tests while the framework automates the generation of the underlying verification infrastructure, making the testbed reusable across different stages of the design flow as the experiments show.